Handbook of European HPC projects


AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems

Project highlights

Energy-efficient heterogeneous supercomputing architectures need to be coupled with a radically new software stack capable of exploiting the benefits offered by the heterogeneity at all the different levels (supercomputer, job, node) to meet the scalability and energy efficiency required by Exascale supercomputers.
ANTAREX will solve these challenging problems by providing a breakthrough approach to express application self-adaptivity at design-time and to runtime manage and autotune applications for green and heterogenous High Performance Computing (HPC) systems up to the Exascale level.

What are anticipated technology (hw/sw/methodology) suggested for inclusion in an EsD project and describe the current maturity?

The compiler technology being developed consists of a separation of concerns (where self-adaptivity and energy efficient strategies are specified aside to application functionalities) promoted using LARA, a Domain Specific Language (DSL) inspired by aspect-oriented programming (AOP) concepts for heterogeneous systems. The project includes the development of standalone libraries, methodologies and tools focused on code analysis and optimization, runtime application autotuning, and resource and power management.

We have different maturity levels among the tools and libraries. The technology behind the DSL has several years of development, the libraries and tools have different levels of maturity (some have started in this project, others started in previous projects and have been extended), and the integration of all the tools and libraries in a single framework is still in development.

The framework is based on the following technologies:

  • The mARGOt autotuner (autotuning framework which enhances the application with an adaptation layer):
  • The Examoon framework (A highly scalable framework for performance and energy monitoring of supercomputing machine in production):
  • The LibVersioningCompiler (easy dynamic compilation with versioning support)
  • The PowerManager (Power capper that selects the best performance point for each core in order to maintain a power constraint while adapting at the workload parallelization strategy):
  • The CLAVA + LARA compiler framework (C/C++ source-to-source tool for code instrumentation and transformations controlled by the LARA language)

How should this technology be used / integrated

The DSL is being used to control the integration between the several libraries/tools and target applications. Other third-party tools and libraries can be used to output information (e.g., resultant from analysis and profiling) to LARA strategies. These LARA strategies can then consider the input information to decide about some code transformations, instrumentation, and autotuning knobs and calls. In addition, with the ANTAREX approach other instrumentation and monitoring libraries and/or autotuning schemes can be holistically integrated by the use of LARA strategies to transform and inject extra code in the application source code.

Are there any pre- or co-requisite items

The approach aims at avoiding manual modifications on source code, so requisites would mostly be writing strategies in the LARA DSL or adapting existing ones. Besides that, the DSL framework (CLAVA) needs a Java runtime, and each tool/library has its own specific dependences.

Any extra work/interaction needed to make them ready?

Some of the technologies in development are already deployed in HPC systems in production, however to have a production-ready framework that integrates all the tools, we consider that it will need extra work beyond the project.

What information / actions are needed to best prepare for EsD projects?

Ensure that each individual component has a clear interface and is well documented, start the integration to have a proof-of-concept and assess the current state, to prepare a plan of what would be necessary to have a fully-fledged product ready for HPC systems.


Cristina Silvano


Coordinating Organization:
Politecnico di Milano, Italy

Project Timespan
2015-09-01 – 2018-11-30

Other Partners:
  • CINECA – Consorzio Interuniversitario, Italy
  • Dompé Farmaceutici SPA, Italy
  • ETHZ – Eidgenössische Technische Hochschule Zürich, Switzerland
  • INRIA – Institut National de Recherche en Informatique et Automatique, France
  • IT4Innovations – VSB – Technical University of Ostrava, Czechia
  • Sygic, Slovakia
  • University of Porto, Portugal