Handbook of European HPC projects

RECIPE

REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems

OBJECTIVE 

The current HPC facilities will need to grow by an order of magnitude in the next few years to reach the Exascale range. The dedicated middleware needed to manage the enormous complexity of future HPC centres, where deep heterogeneity is needed to handle the wide variety of applications within reasonable power budgets, will be one of the most critical aspects in the evolution of HPC infrastructure towards Exascale. This middleware will need to address the critical issue of reliability in face of the increasing number of resources, and therefore decreasing mean time between failures. 

To close this gap, RECIPE provides: a hierarchical runtime resource management infra-structure optimizing energy efficiency and ensuring reliability for both time-critical and throughput-oriented computation; a predictive reliability methodology to support the enforcing of QoS guarantees in face of both transient and long-term hardware failures, including thermal, timing and reliability mod-els; and a set of integration layers allowing the resource manager to interact with both the application and the underlying deeply heterogeneous architecture, addressing them in a disaggregate way. 

Quantitative goals for RECIPE include: 25% increase in energy efficiency (performance/watt) with an 15% MTTF improvement due to proactive thermal management; energy-delay product improved up to 25%; 20% reduction of faulty executions. 

The project will assess its results against the following set of real world use cases, addressing key application domains ranging from well-established HPC applications such as geophysical exploration and meteorology, to emerging application domains such as bio-medical machine learning and data analytics. 

To this end, RECIPE relies on a consortium composed of four leading academic partners (POLIMI, UPV, EPFL, CeRICT); two supercomputing centres, BSC and PSNC; a research hospital, CHUV, and an SME, IBTS, which provide effective exploitation avenues through industry-based use cases. 

The RECIPE Hardware-Software Stack 

PROJECT’S CONTACT:

William Fornaciari

Transition to Exascale Computing

Call:
FETHPC-02-2017

Coordinating Organization:
Politecnico di Milano, Italy

Project Timespan
2018-05-01 – 2021-10-31

Other Partners:
  • Universitat Politècnica de València UPV, Spain
  • CeRICT – Centro Regionale Information Communication Technology scrl, Italy
  • BSC – Barcelona Supercomputing Center, Spain
  • Instytut Chemii Bioorganicznej Polskiej Akademii Nauk – Poznań Supercomputing and Networking Center (PSNC), Poland
  • EPFL – Ecole Polytechnique Fédérale de Lausanne, Switzerland
  • IBTS – Intelligence behind Things Solutions SRL, Italy
  • CHUV – Centre Hospitalier Universitaire Vaudois, Switzerland